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58 lines
1.8 KiB
58 lines
1.8 KiB
// ======================================================================
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// DES encryption/decryption
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// algorithm according to FIPS 46-3 specification
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// Copyright (C) 2007 Torsten Meissner
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//-----------------------------------------------------------------------
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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// ======================================================================
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module des
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(
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input reset_i, // async reset
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input clk_i, // clock
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input mode_i, // des-mode: 0 = encrypt, 1 = decrypt
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input [0:63] key_i, // key input
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input [0:63] data_i, // data input
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input valid_i, // input key/data valid flag
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output [0:63] data_o, // data output
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output valid_o // output data valid flag
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);
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`include "../../rtl/verilog/des_pkg.v"
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reg [0:17] valid;
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reg [0:16] mode;
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wire valid_o = valid[17];
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always @(posedge clk_i, negedge reset_i) begin
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if(~reset_i) begin
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valid <= 0;
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end
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else begin
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// shift registers
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valid[1:17] <= valid[0:16];
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valid[0] <= valid_i;
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mode[1:16] <= mode[0:15];
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mode[0] <= mode_i;
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end
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end
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endmodule
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