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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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132
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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45c9409572
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cryptocores
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tdes
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sim
History
T. Meissner
5fff1d89d1
initial commit of verilog simulation environment for tdes core
12 years ago
..
verilog
initial commit of verilog simulation environment for tdes core
12 years ago
vhdl
adapt makefile to new directory structure; new variable SRC_FILES for vhdl sources
12 years ago