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cbcmac_des.vhd 4.0KB

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  1. -- ======================================================================
  2. -- CBC-MAC-DES
  3. -- Copyright (C) 2015 Torsten Meissner
  4. -------------------------------------------------------------------------
  5. -- This program is free software; you can redistribute it and/or modify
  6. -- it under the terms of the GNU General Public License as published by
  7. -- the Free Software Foundation; either version 2 of the License, or
  8. -- (at your option) any later version.
  9. -- This program is distributed in the hope that it will be useful,
  10. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. -- GNU General Public License for more details.
  13. -- You should have received a copy of the GNU General Public License
  14. -- along with this program; if not, write to the Free Software
  15. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  16. -- ======================================================================
  17. library ieee;
  18. use ieee.std_logic_1164.all;
  19. use ieee.numeric_std.all;
  20. use work.des_pkg.all;
  21. entity cbcmac_des is
  22. port (
  23. reset_i : in std_logic; -- low active async reset
  24. clk_i : in std_logic; -- clock
  25. start_i : in std_logic; -- start cbc
  26. key_i : in std_logic_vector(0 to 63); -- key input
  27. data_i : in std_logic_vector(0 to 63); -- data input
  28. valid_i : in std_logic; -- input key/data valid flag
  29. accept_o : out std_logic; -- input accept
  30. data_o : out std_logic_vector(0 tO 63); -- data output
  31. valid_o : out std_logic; -- output data valid flag
  32. accept_i : in std_logic -- output accept
  33. );
  34. end entity cbcmac_des;
  35. architecture rtl of cbcmac_des is
  36. component des is
  37. generic (
  38. design_type : string := "ITER"
  39. );
  40. port (
  41. reset_i : in std_logic;
  42. clk_i : in std_logic;
  43. mode_i : in std_logic;
  44. key_i : in std_logic_vector(0 to 63);
  45. data_i : in std_logic_vector(0 to 63);
  46. valid_i : in std_logic;
  47. accept_o : out std_logic;
  48. data_o : out std_logic_vector(0 to 63);
  49. valid_o : out std_logic;
  50. accept_i : in std_logic
  51. );
  52. end component des;
  53. -- CBCMAC must have fix IV for security reasons
  54. constant C_IV : std_logic_vector(0 to 63) := (others => '0');
  55. signal s_des_datain : std_logic_vector(0 to 63);
  56. signal s_des_dataout : std_logic_vector(0 to 63);
  57. signal s_des_dataout_d : std_logic_vector(0 to 63);
  58. signal s_des_key : std_logic_vector(0 to 63);
  59. signal s_key : std_logic_vector(0 to 63);
  60. signal s_des_accept : std_logic;
  61. signal s_des_validout : std_logic;
  62. begin
  63. s_des_datain <= C_IV xor data_i when start_i = '1' else
  64. s_des_dataout_d xor data_i;
  65. data_o <= s_des_dataout;
  66. s_des_key <= key_i when start_i = '1' else s_key;
  67. accept_o <= s_des_accept;
  68. valid_o <= s_des_validout;
  69. inputregister : process(clk_i, reset_i) is
  70. begin
  71. if(reset_i = '0') then
  72. s_key <= (others => '0');
  73. elsif(rising_edge(clk_i)) then
  74. if(valid_i = '1' and s_des_accept = '1' and start_i = '1') then
  75. s_key <= key_i;
  76. end if;
  77. end if;
  78. end process inputregister;
  79. outputregister : process(clk_i, reset_i) is
  80. begin
  81. if(reset_i = '0') then
  82. s_des_dataout_d <= (others => '0');
  83. elsif(rising_edge(clk_i)) then
  84. if(s_des_validout = '1') then
  85. s_des_dataout_d <= s_des_dataout;
  86. end if;
  87. end if;
  88. end process outputregister;
  89. i_des : des
  90. generic map (
  91. design_type => "ITER"
  92. )
  93. port map (
  94. reset_i => reset_i,
  95. clk_i => clk_i,
  96. mode_i => '0',
  97. key_i => s_des_key,
  98. data_i => s_des_datain,
  99. valid_i => valid_i,
  100. accept_o => s_des_accept,
  101. data_o => s_des_dataout,
  102. valid_o => s_des_validout,
  103. accept_i => accept_i
  104. );
  105. end architecture rtl;