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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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112
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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553e105986
master
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cryptocores
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aes
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sim
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vhdl
History
Torsten Meissner
455bcaa289
ovl standard enable, fixed minor bug in pkg
13 years ago
..
makefile
ovl standard enable, fixed minor bug in pkg
13 years ago
tb_aes.tcl
partition design in ovl and not ovl enabled
13 years ago
tb_aes.vhd
partition design in ovl and not ovl enabled
13 years ago
tb_aes_ovl.vhd
partition design in ovl and not ovl enabled
13 years ago