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129 lines
3.1 KiB
129 lines
3.1 KiB
// ======================================================================
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// TDES encryption/decryption
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// algorithm according:FIPS 46-3 specification
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// Copyright (C) 2012 Torsten Meissner
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//-----------------------------------------------------------------------
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write:the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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// ======================================================================
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`timescale 1ns/1ps
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module tdes
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(
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input reset_i, // async reset
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input clk_i, // clock
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input mode_i, // des-mode: 0 = encrypt, 1 = decrypt
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input [0:63] key1_i, // key input
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input [0:63] key2_i // key input
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input [0:63] key3_i // key input
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input [0:63] data_i, // data input
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input valid_i, // input key/data valid flag
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output reg [0:63] data_o, // data output
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output valid_o, // output data valid flag
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output reg ready_o // ready for new data
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);
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`include "../../rtl/verilog/des.v"
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reg reset;
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reg mode;
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reg [0:63] key1;
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reg [0:63] key2;
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reg [0:63] key3;
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reg ready_o;
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// input register
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always @(posedge clk_i, negedge reset_i) begin
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if (~reset_i) begin
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reset <= 0;
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mode <= 0;
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key1 <= 0;
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key2 <= 0;
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key3 <= 0;
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end
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else begin
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reset <= reset_i;
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if (valid_i && ready_o) begin
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mode <= mode_i;
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key1 <= key1_i;
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key2 <= key2_i;
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key3 <= key3_i;
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end
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end
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end
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// output register
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always @(posedge clk_i, negedge reset_i) begin
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if (~reset_i) begin
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ready_o <= 0;
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end
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else begin
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if (valid_i && ready_o) begin
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ready_o <= 0;
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end
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if (valid_o || (reset_i && ~reset)) begin
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ready_o <= 1;
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end
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end
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end
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des : i1_des
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(
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.reset_i(reset_i),
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.clk_i(clk_i),
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.mode_i(mode_i),
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.key_i(des1_key),
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.data_i(data_i),
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.valid_i(des1_validin),
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.data_o(des1_dataout),
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.valid_o(des1_validout)
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);
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des : i2_des
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(
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.reset_i(reset_i),
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.clk_i(clk_i),
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.mode_i(des2_mode),
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.key_i(key2),
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.data_i(des1_dataout),
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.valid_i(des1_validout),
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.data_o(des2_dataout),
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.valid_o(des2_validout)
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);
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des : i3_des
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(
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.reset_i(reset_i),
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.clk_i(clk_i),
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.mode_i(mode_i),
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.key_i(des1_key),
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.data_i(des2_dataout),
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.valid_i(des2_validout),
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.data_o(data_o),
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.valid_o(valid_o)
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);
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endmodule
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