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444 lines
10 KiB
444 lines
10 KiB
// ======================================================================
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// DES encryption/decryption
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// algorithm according:FIPS 46-3 specification
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// Copyright (C) 2012 Torsten Meissner
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//-----------------------------------------------------------------------
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write:the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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// ======================================================================
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module des
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(
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input reset_i, // async reset
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input clk_i, // clock
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input mode_i, // des-mode: 0 = encrypt, 1 = decrypt
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input [0:63] key_i, // key input
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input [0:63] data_i, // data input
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input valid_i, // input key/data valid flag
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output reg [0:63] data_o, // data output
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output valid_o // output data valid flag
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);
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`include "../../rtl/verilog/des_pkg.v"
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// valid, mode register
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reg [0:17] valid;
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reg [0:16] mode;
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// algorithm pipeline register
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// key calculation register
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reg [0:27] c0;
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reg [0:27] c1;
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reg [0:27] c2;
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reg [0:27] c3;
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reg [0:27] c4;
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reg [0:27] c5;
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reg [0:27] c6;
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reg [0:27] c7;
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reg [0:27] c8;
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reg [0:27] c9;
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reg [0:27] c10;
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reg [0:27] c11;
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reg [0:27] c12;
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reg [0:27] c13;
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reg [0:27] c14;
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reg [0:27] c15;
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reg [0:27] c16;
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reg [0:27] d0;
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reg [0:27] d1;
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reg [0:27] d2;
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reg [0:27] d3;
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reg [0:27] d4;
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reg [0:27] d5;
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reg [0:27] d6;
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reg [0:27] d7;
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reg [0:27] d8;
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reg [0:27] d9;
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reg [0:27] d10;
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reg [0:27] d11;
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reg [0:27] d12;
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reg [0:27] d13;
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reg [0:27] d14;
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reg [0:27] d15;
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reg [0:27] d16;
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// key register
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reg [0:47] key1;
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reg [0:47] key2;
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reg [0:47] key3;
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reg [0:47] key4;
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reg [0:47] key5;
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reg [0:47] key6;
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reg [0:47] key7;
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reg [0:47] key8;
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reg [0:47] key9;
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reg [0:47] key10;
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reg [0:47] key11;
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reg [0:47] key12;
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reg [0:47] key13;
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reg [0:47] key14;
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reg [0:47] key15;
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reg [0:47] key16;
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// register for left, right data blocks
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reg [0:31] l0;
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reg [0:31] l1;
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reg [0:31] l2;
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reg [0:31] l3;
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reg [0:31] l4;
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reg [0:31] l5;
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reg [0:31] l6;
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reg [0:31] l7;
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reg [0:31] l8;
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reg [0:31] l9;
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reg [0:31] l10;
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reg [0:31] l11;
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reg [0:31] l12;
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reg [0:31] l13;
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reg [0:31] l14;
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reg [0:31] l15;
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reg [0:31] l16;
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reg [0:31] r0;
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reg [0:31] r1;
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reg [0:31] r2;
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reg [0:31] r3;
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reg [0:31] r4;
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reg [0:31] r5;
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reg [0:31] r6;
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reg [0:31] r7;
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reg [0:31] r8;
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reg [0:31] r9;
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reg [0:31] r10;
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reg [0:31] r11;
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reg [0:31] r12;
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reg [0:31] r13;
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reg [0:31] r14;
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reg [0:31] r15;
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reg [0:31] r16;
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wire valid_o = valid[17];
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// valid, mode register
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always @(posedge clk_i, negedge reset_i) begin
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if(~reset_i) begin
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valid <= 0;
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end
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else begin
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// shift registers
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valid[1:17] <= valid[0:16];
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valid[0] <= valid_i;
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mode[1:16] <= mode[0:15];
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mode[0] <= mode_i;
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end
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end
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// des algorithm pipeline
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always @(posedge clk_i, negedge reset_i) begin
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if(~reset_i) begin
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c0 <= 0;
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c1 <= 0;
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c2 <= 0;
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c3 <= 0;
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c4 <= 0;
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c5 <= 0;
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c6 <= 0;
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c7 <= 0;
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c8 <= 0;
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c9 <= 0;
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c10 <= 0;
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c11 <= 0;
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c12 <= 0;
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c13 <= 0;
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c14 <= 0;
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c15 <= 0;
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c16 <= 0;
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d0 <= 0;
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d1 <= 0;
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d2 <= 0;
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d3 <= 0;
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d4 <= 0;
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d5 <= 0;
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d6 <= 0;
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d7 <= 0;
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d8 <= 0;
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d9 <= 0;
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d10 <= 0;
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d11 <= 0;
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d12 <= 0;
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d13 <= 0;
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d14 <= 0;
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d15 <= 0;
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d16 <= 0;
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key1 <= 0;
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key2 <= 0;
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key3 <= 0;
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key4 <= 0;
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key5 <= 0;
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key6 <= 0;
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key7 <= 0;
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key8 <= 0;
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key9 <= 0;
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key10 <= 0;
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key11 <= 0;
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key12 <= 0;
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key13 <= 0;
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key14 <= 0;
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key15 <= 0;
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key16 <= 0;
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l0 <= 0;
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l1 <= 0;
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l2 <= 0;
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l3 <= 0;
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l4 <= 0;
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l5 <= 0;
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l6 <= 0;
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l7 <= 0;
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l8 <= 0;
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l9 <= 0;
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l10 <= 0;
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l11 <= 0;
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l12 <= 0;
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l13 <= 0;
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l14 <= 0;
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l15 <= 0;
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l16 <= 0;
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r0 <= 0;
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r1 <= 0;
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r2 <= 0;
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r3 <= 0;
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r4 <= 0;
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r5 <= 0;
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r6 <= 0;
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r7 <= 0;
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r8 <= 0;
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r9 <= 0;
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r10 <= 0;
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r11 <= 0;
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r12 <= 0;
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r13 <= 0;
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r14 <= 0;
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r15 <= 0;
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r16 <= 0;
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data_o <= 0;
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end
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else begin
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// output stage
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data_o <= ipn({r16, l16});
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// 16. stage
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if (mode[16] == 1'b0) begin
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c16 = {c15[1:27], c15[0]};
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d16 = {d15[1:27], d15[0]};
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end
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else begin
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c16 = {c15[27], c15[0:26]};
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d16 = {d15[27], d15[0:26]};
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end
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key16 = pc2({c16, d16});
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l16 = r15;
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r16 = l15 ^ (f(r15, key16));
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// 15. stage
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if (mode[15] == 1'b0) begin
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c15 = {c14[2:27], c14[0:1]};
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d15 = {d14[2:27], d14[0:1]};
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end
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else begin
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c15 = {c14[26:27], c14[0:25]};
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d15 = {d14[26:27], d14[0:25]};
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end
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key15 = pc2({c15, d15});
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l15 = r14;
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r15 = l14 ^ (f(r14, key15));
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// 14. stage
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if (mode[14] == 1'b0) begin
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c14 = {c13[2:27], c13[0:1]};
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d14 = {d13[2:27], d13[0:1]};
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end
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else begin
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c14 = {c13[26:27], c13[0:25]};
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d14 = {d13[26:27], d13[0:25]};
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end
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key14 = pc2({c14, d14});
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l14 = r13;
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r14 = l13 ^ (f(r13, key14));
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// 13. stage
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if (mode[13] == 1'b0) begin
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c13 = {c12[2:27], c12[0:1]};
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d13 = {d12[2:27], d12[0:1]};
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end
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else begin
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c13 = {c12[26:27], c12[0:25]};
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d13 = {d12[26:27], d12[0:25]};
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end
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key13 = pc2({c13, d13});
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l13 = r12;
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r13 = l12 ^ (f(r12, key13));
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// 12. stage
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if (mode[12] == 1'b0) begin
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c12 = {c11[2:27], c11[0:1]};
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d12 = {d11[2:27], d11[0:1]};
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end
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else begin
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c12 = {c11[26:27], c11[0:25]};
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d12 = {d11[26:27], d11[0:25]};
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end
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key12 = pc2({c12, d12});
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l12 = r11;
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r12 = l11 ^ (f(r11, key12));
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/*// 11. stage
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if (mode[11] == 1'b0) begin
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c11 = c10(2:27], c10(0:1];
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d11 = d10(2:27], d10(0:1];
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end
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else begin
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c11 = c10(26:27], c10(0:25];
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d11 = d10(26:27], d10(0:25];
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end
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key11 = pc2( ( c11, d11 ) ];
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l11 = r10;
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r11 = l10 ^ ( f( r10, key11 ) ];
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// 10. stage
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if (mode[10] == 1'b0) begin
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c10 = c9(2:27], c9(0:1];
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d10 = d9(2:27], d9(0:1];
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end
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else begin
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c10 = c9(26:27], c9(0:25];
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d10 = d9(26:27], d9(0:25];
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end
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key10 = pc2( ( c10, d10 ) ];
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l10 = r9;
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r10 = l9 ^ ( f( r9, key10 ) ];
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// 9. stage
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if (mode[9] == 1'b0) begin
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c9 = c8(1:27], c8(0];
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d9 = d8(1:27], d8(0];
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end
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else begin
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c9 = c8(27], c8(0:26];
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d9 = d8(27], d8(0:26];
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end
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key9 = pc2( ( c9, d9 ) ];
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l9 = r8;
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r9 = l8 ^ ( f( r8, key9 ) ];
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// 8. stage
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if (mode[8] == 1'b0) begin
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c8 = c7(2:27], c7(0:1];
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d8 = d7(2:27], d7(0:1];
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end
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else begin
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c8 = c7(26:27], c7(0:25];
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d8 = d7(26:27], d7(0:25];
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end
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key8 = pc2( ( c8, d8 ) ];
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l8 = r7;
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r8 = l7 ^ ( f( r7, key8 ) ];
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// 7. stage
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if (mode[7] == 1'b0) begin
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c7 = c6(2:27], c6(0:1];
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d7 = d6(2:27], d6(0:1];
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end
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else begin
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c7 = c6(26:27], c6(0:25];
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d7 = d6(26:27], d6(0:25];
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end
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key7 = pc2( ( c7, d7 ) ];
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l7 = r6;
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r7 = l6 ^ ( f( r6, key7 ) ];
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// 6. stage
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if (mode[6] == 1'b0) begin
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c6 = c5(2:27], c5(0:1];
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d6 = d5(2:27], d5(0:1];
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end
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else begin
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c6 = c5(26:27], c5(0:25];
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d6 = d5(26:27], d5(0:25];
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end
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key6 = pc2( ( c6, d6 ) ];
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l6 = r5;
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r6 = l5 ^ ( f( r5, key6 ) ];
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// 5. stage
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if (mode[5] == 1'b0) begin
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c5 = c4(2:27], c4(0:1];
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d5 = d4(2:27], d4(0:1];
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end
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else begin
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c5 = {c4[26:27], c4(0:25];
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d5 = {d4[26:27], d4(0:25];
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end
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key5 = pc2({c5, d5});
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l5 = r4;
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r5 = l4 ^ (f(r4, key5));
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// 4. stage
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if (mode[4] == 1'b0) begin
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c4 = c3[2:27], c3[0:1]};
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d4 = d3[2:27], d3[0:1]};
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end
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else begin
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c4 = {c3[26:27], c3[0:25]};
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d4 = {d3[26:27], d3[0:25]};
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end
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key4 = pc2({c4, d4}];
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l4 = r3;
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r4 = l3 ^ (f(r3, key4)];
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// 3. stage
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if (mode[3] == 1'b0) begin
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c3 = {c2[2:27], c2[0:1]};
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d3 = {d2[2:27], d2[0:1]};
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end
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else begin
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c3 = {c2[26:27], c2[0:25]};
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d3 = {d2[26:27], d2[0:25]};
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end
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key3 = pc2({c3, d3}];
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l3 = r2;
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r3 = l2 ^ (f(r2, key3)];*/
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// 2. stage
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if (mode[2] == 1'b0) begin
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c2 = {c1[1:27], c1[0]};
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d2 = {d1[1:27], d1[0]};
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end
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else begin
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c2 = {c1[27], c1[0:26]};
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d2 = {d1[27], d1[0:26]};
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end
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key2 = pc2({c2, d2});
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l2 = r1;
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r2 = l1 ^ (f(r1, key2));
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// 1. stage
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if (mode[1] == 1'b0) begin
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c1 = {c0[1:27], c0[0]};
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d1 = {d0[1:27], d0[0]};
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end
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else begin
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c1 = c0;
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d1 = d0;
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end
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key1 = pc2({c1, d1});
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l1 = r0;
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r1 = l0 ^ (f(r0, key1));
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// input stage
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l0 = ip0(data_i);
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r0 = ip0(data_i);
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c0 = pc1_c(key_i);
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d0 = pc1_d(key_i);
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end
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end
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endmodule
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