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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
73
Commits
1
Branch
1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
Tree:
69c7fe92f9
cryptocores
/
aes
/
rtl
History
Torsten Meissner
78db757f9d
new verily version of ads, startup code only at the moment
13 years ago
..
verilog
new verily version of ads, startup code only at the moment
13 years ago
vhdl
ovl standard enable, fixed minor bug in pkg
13 years ago