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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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89
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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cryptocores
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des
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rtl
History
T. Meissner
ccf8140132
complete refactoring of the des verilog code
* now 2 seperate processes: key scheduling & data path * keys are now concurrent wire assignments
12 years ago
..
verilog
complete refactoring of the des verilog code
12 years ago
vhdl
Revert "dasdsad"
13 years ago