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159 lines
5.0 KiB
159 lines
5.0 KiB
-- ======================================================================
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-- DES encryption/decryption
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-- algorithm according to FIPS 46-3 specification
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-- Copyright (C) 2011 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- the testvectors in this file are taken from the project
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-- "DES/Triple DES IP Cores" from Rudolf Usselmann, to find under
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-- http://opencores.org/project,des
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-- Copyright (C) 2001 Rudolf Usselmann (rudi@asics.ws)
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-- ======================================================================
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-- Revision 1.0 2011/09/17
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-- Initial release
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.ALL;
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entity tb_des is
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end entity tb_des;
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architecture rtl of tb_des is
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type t_array is array (0 to 18) of std_logic_vector(0 to 63);
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signal s_key_values : t_array :=
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(x"7CA110454A1A6E57", x"0131D9619DC1376E", x"07A1133E4A0B2686",
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x"3849674C2602319E", x"04B915BA43FEB5B6", x"0113B970FD34F2CE",
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x"0170F175468FB5E6", x"43297FAD38E373FE", x"07A7137045DA2A16",
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x"04689104C2FD3B2F", x"37D06BB516CB7546", x"1F08260D1AC2465E",
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x"584023641ABA6176", x"025816164629B007", x"49793EBC79B3258F",
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x"4FB05E1515AB73A7", x"49E95D6D4CA229BF", x"018310DC409B26D6",
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x"1C587F1C13924FEF");
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signal s_plain_values : t_array :=
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(x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172",
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x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A",
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x"0756D8E0774761D2", x"762514B829BF486A", x"3BDD119049372802",
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x"26955F6835AF609A", x"164D5E404F275232", x"6B056E18759F5CCA",
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x"004BD6EF09176062", x"480D39006EE762F2", x"437540C8698F3CFA",
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x"072D43A077075292", x"02FE55778117F12A", x"1D9D5C5018F728C2",
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x"305532286D6F295A");
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signal s_crypt_values : t_array :=
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(x"690F5B0D9A26939B", x"7A389D10354BD271", x"868EBB51CAB4599A",
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x"7178876E01F19B2A", x"AF37FB421F8C4095", x"86A560F10EC6D85B",
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x"0CD3DA020021DC09", x"EA676B2CB7DB2B7A", x"DFD64A815CAF1A0F",
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x"5C513C9C4886C088", x"0A2AEEAE3FF4AB77", x"EF1BF03E5DFA575A",
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x"88BF0DB6D70DEE56", x"A1F9915541020B56", x"6FBF1CAFCFFD0556",
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x"2F22E49BAB7CA1AC", x"5A6B612CC26CCE4A", x"5F4C038ED12B2E41",
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x"63FAC0D034D9F793");
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signal s_clk : std_logic := '0';
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signal s_mode : std_logic := '0';
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signal s_key : std_logic_vector(0 to 63) := (others => '0');
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signal s_datain : std_logic_vector(0 to 63) := (others => '0');
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signal s_validin : std_logic := '0';
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signal s_dataout : std_logic_vector(0 to 63);
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signal s_validout : std_logic;
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component des is
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port (
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clk_i : in std_logic;
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mode_i : in std_logic;
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key_i : in std_logic_vector(0 TO 63);
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data_i : in std_logic_vector(0 TO 63);
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valid_i : in std_logic;
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data_o : out std_logic_vector(0 TO 63);
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valid_o : out std_logic
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);
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end component des;
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begin
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s_clk <= not(s_clk) after 10 ns;
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teststimuliP : process is
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begin
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report "# encryption test";
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for index in 0 to 18 loop
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wait until rising_edge(s_clk);
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s_mode <= '0';
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s_validin <= '1';
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s_key <= s_key_values(index);
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s_datain <= s_plain_values(index);
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end loop;
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wait until rising_edge(s_clk);
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s_validin <= '0';
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wait for 100 ns;
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report "# decryption test";
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for index in 0 to 18 loop
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wait until rising_edge(s_clk);
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s_mode <= '1';
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s_validin <= '1';
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s_key <= s_key_values(index);
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s_datain <= s_crypt_values(index);
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end loop;
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wait until rising_edge(s_clk);
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s_mode <= '0';
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s_validin <= '0';
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wait;
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end process teststimuliP;
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testcheckerP : process is
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begin
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for index in 0 to 18 loop
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wait until rising_edge(s_clk) and s_validout = '1';
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if(s_dataout /= s_crypt_values(index)) then
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report "encryption error";
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end if;
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end loop;
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for index in 0 to 18 loop
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wait until rising_edge(s_clk) and s_validout = '1';
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if(s_dataout /= s_plain_values(index)) then
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report "decryption error";
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end if;
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end loop;
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wait;
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end process testcheckerP;
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i_des : des
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port map (
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clk_i => s_clk,
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mode_i => s_mode,
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key_i => s_key,
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data_i => s_datain,
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valid_i => s_validin,
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data_o => s_dataout,
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valid_o => s_validout
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);
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end architecture rtl;
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