cryptography ip-cores in vhdl / verilog
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cryptography

aes_dec.vhd 5.4KB

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  1. -- ======================================================================
  2. -- AES encryption/decryption
  3. -- Copyright (C) 2019 Torsten Meissner
  4. -------------------------------------------------------------------------
  5. -- This program is free software; you can redistribute it and/or modify
  6. -- it under the terms of the GNU General Public License as published by
  7. -- the Free Software Foundation; either version 2 of the License, or
  8. -- (at your option) any later version.
  9. -- This program is distributed in the hope that it will be useful,
  10. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. -- GNU General Public License for more details.
  13. -- You should have received a copy of the GNU General Public License
  14. -- along with this program; if not, write to the Free Software
  15. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  16. -- ======================================================================
  17. library ieee;
  18. use ieee.std_logic_1164.all;
  19. use ieee.numeric_std.all;
  20. use work.aes_pkg.all;
  21. entity aes_dec is
  22. generic (
  23. design_type : string := "ITER"
  24. );
  25. port (
  26. reset_i : in std_logic; -- async reset
  27. clk_i : in std_logic; -- clock
  28. key_i : in std_logic_vector(0 to 127); -- key input
  29. data_i : in std_logic_vector(0 to 127); -- data input
  30. valid_i : in std_logic; -- input key/data valid flag
  31. accept_o : out std_logic;
  32. data_o : out std_logic_vector(0 to 127); -- data output
  33. valid_o : out std_logic; -- output data valid flag
  34. accept_i : in std_logic
  35. );
  36. end entity aes_dec;
  37. architecture rtl of aes_dec is
  38. -- Fixed round keys for verification until key schedule is implemented
  39. type t_key_array is array (11 downto 1) of t_key;
  40. constant c_round_keys : t_key_array := (
  41. (x"2b7e1516", x"28aed2a6", x"abf71588", x"09cf4f3c"),
  42. (x"a0fafe17", x"88542cb1", x"23a33939", x"2a6c7605"),
  43. (x"f2c295f2", x"7a96b943", x"5935807a", x"7359f67f"),
  44. (x"3d80477d", x"4716fe3e", x"1e237e44", x"6d7a883b"),
  45. (x"ef44a541", x"a8525b7f", x"b671253b", x"db0bad00"),
  46. (x"d4d1c6f8", x"7c839d87", x"caf2b8bc", x"11f915bc"),
  47. (x"6d88a37a", x"110b3efd", x"dbf98641", x"ca0093fd"),
  48. (x"4e54f70e", x"5f5fc9f3", x"84a64fb2", x"4ea6dc4f"),
  49. (x"ead27321", x"b58dbad2", x"312bf560", x"7f8d292f"),
  50. (x"ac7766f3", x"19fadc21", x"28d12941", x"575c006e"),
  51. (x"d014f9a8", x"c9ee2589", x"e13f0cc8", x"b6630ca6")
  52. );
  53. signal s_round_key : t_key := (others => (others => '0'));
  54. begin
  55. -- psl default clock is rising_edge(Clk_i);
  56. IterG : if design_type = "ITER" generate
  57. signal s_round : t_dec_rounds;
  58. begin
  59. s_round_key <= c_round_keys(s_round) when s_round >= 1 and s_round <= 11 else
  60. (others => (others => '0'));
  61. DeCryptP : process (reset_i, clk_i) is
  62. variable v_state : t_datatable2d;
  63. begin
  64. if (reset_i = '0') then
  65. v_state := (others => (others => (others => '0')));
  66. s_round <= 0;
  67. accept_o <= '0';
  68. data_o <= (others => '0');
  69. valid_o <= '0';
  70. elsif (rising_edge(clk_i)) then
  71. case s_round is
  72. when 0 =>
  73. accept_o <= '1';
  74. if (accept_o = '1' and valid_i = '1') then
  75. accept_o <= '0';
  76. v_state := set_state(data_i);
  77. s_round <= s_round + 1;
  78. end if;
  79. when 1 =>
  80. v_state := addroundkey(v_state, s_round_key);
  81. s_round <= s_round + 1;
  82. when t_dec_rounds'high-1 =>
  83. v_state := invshiftrow(v_state);
  84. v_state := invsubbytes(v_state);
  85. v_state := addroundkey(v_state, s_round_key);
  86. s_round <= s_round + 1;
  87. -- set data & valid to save one cycle
  88. valid_o <= '1';
  89. data_o <= get_state(v_state);
  90. when t_dec_rounds'high =>
  91. if (valid_o = '1' and accept_i = '1') then
  92. valid_o <= '0';
  93. data_o <= (others => '0');
  94. s_round <= 0;
  95. -- Set accept to save one cycle
  96. accept_o <= '1';
  97. end if;
  98. when others =>
  99. v_state := invshiftrow(v_state);
  100. v_state := invsubbytes(v_state);
  101. v_state := addroundkey(v_state, s_round_key);
  102. v_state := invmixcolumns(v_state);
  103. s_round <= s_round + 1;
  104. end case;
  105. end if;
  106. end process DeCryptP;
  107. -- synthesis off
  108. verification : block is
  109. signal s_data : std_logic_vector(0 to 127);
  110. begin
  111. s_data <= data_o when rising_edge(clk_i) else
  112. 128x"0" when reset_i = '0';
  113. -- psl cover accept_o;
  114. -- psl assert always (accept_o -> s_round = 0);
  115. -- psl cover valid_i and accept_o;
  116. -- psl assert always (valid_i and accept_o -> next not accept_o);
  117. -- psl cover valid_o;
  118. -- psl assert always (valid_o -> s_round = t_dec_rounds'high);
  119. -- psl cover valid_o and accept_i;
  120. -- psl assert always (valid_o and accept_i -> next not valid_o);
  121. -- psl cover valid_o and not accept_i;
  122. -- psl assert always (valid_o and not accept_i -> next valid_o);
  123. -- psl assert always (valid_o and not accept_i -> next data_o = s_data);
  124. end block verification;
  125. -- synthesis on
  126. end generate IterG;
  127. end architecture rtl;