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cryptography ip-cores in vhdl / verilog
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cryptocores/cbctdes/sim/verilog
T. Meissner 2a2aa23e21 wait for rising edge of reset before send stimuli data 11 years ago
..
makefile added verilog simulation environment 11 years ago
tb_cbctdes.v wait for rising edge of reset before send stimuli data 11 years ago
test_data.txt added verilog simulation environment 11 years ago