cryptography ip-cores in vhdl / verilog
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Torsten Meissner 9ff075be14 Revision 1.0.2 2011/09/18 13 years ago
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makefile set assertion level for ghdl to 'error', expanded simulation time to 7us 13 years ago
tb_des.vhd Revision 1.0.2 2011/09/18 13 years ago