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cryptography ip-cores in vhdl / verilog
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cryptocores/des
Torsten Meissner b08ff1f872 set assertion level for ghdl to 'error', expanded simulation time to 7us 13 years ago
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rtl added ip-core: des algorithm as described in fips document 46-3 13 years ago
sim set assertion level for ghdl to 'error', expanded simulation time to 7us 13 years ago