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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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123
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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b6fdf6bbd4
master
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cryptocores
/
cbcdes
/
rtl
/
verilog
History
T. Meissner
4489748aec
initial commit os CBCDES verilog design file
12 years ago
..
cbcdes.v
initial commit os CBCDES verilog design file
12 years ago
des.v
import verilog des design files from des project
12 years ago
des_pkg.v
import verilog des design files from des project
12 years ago