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189 lines
4.3 KiB
189 lines
4.3 KiB
// ======================================================================
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// DES encryption/decryption testbench
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// tests according to NIST 800-17 special publication
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// Copyright (C) 2012 Torsten Meissner
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//-----------------------------------------------------------------------
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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// ======================================================================
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`timescale 1ns/1ps
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module tb_tdes;
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// set dumpfile
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initial begin
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$dumpfile ("tb_tdes.vcd");
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$dumpvars (0, tb_tdes);
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end
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reg reset;
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reg clk = 0;
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reg mode;
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reg [0:63] key1;
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reg [0:63] key2;
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reg [0:63] key3;
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reg [0:63] datain;
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reg validin;
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integer index;
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integer outdex;
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integer errors;
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wire [0:63] dataout;
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wire validout;
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wire ready;
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reg [0:63] test_data [0:18];
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reg [0:63] test_answers [0:18];
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// read in test data files
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initial begin
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$readmemh("test_data.txt", test_data);
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end
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// setup simulation
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initial begin
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reset = 1;
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#1 reset = 0;
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#20 reset = 1;
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end
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// generate clock with 100 mhz
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always #5 clk = !clk;
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// init the register values
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initial
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forever @(negedge reset) begin
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//disable stimuli;
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disable checker;
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mode <= 0;
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validin <= 0;
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key1 <= 0;
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key2 <= 0;
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key3 <= 0;
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datain <= 0;
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errors = 0;
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end
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// stimuli generator process
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initial
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forever @(negedge reset) begin
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index = 0;
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while (index < 19) begin
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@(posedge clk)
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if (ready) begin
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mode <= 0;
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validin <= 1;
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datain <= test_data[index];
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key1 <= 64'h1111111111111111;
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key2 <= 64'h5555555555555555;
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key3 <= 64'h9999999999999999;
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index = index + 1;
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@(posedge clk)
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validin <= 0;
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end
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end
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index = 0;
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while (index < 19) begin
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@(posedge clk)
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if (ready) begin
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mode <= 1;
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validin <= 1;
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datain <= test_answers[index];
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key1 <= 64'h1111111111111111;
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key2 <= 64'h5555555555555555;
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key3 <= 64'h9999999999999999;
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index = index + 1;
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@(posedge clk)
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validin <= 0;
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end
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end
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@(posedge clk)
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validin <= 0;
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mode <= 0;
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datain <= 0;
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key1 <= 0;
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key2 <= 0;
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key3 <= 0;
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end
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// checker process
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always begin : checker
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wait (reset)
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outdex = 0;
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// encryption tests
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outdex = 0;
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while (outdex < 19) begin
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@(posedge clk)
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if (validout) begin
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test_answers[outdex] = dataout;
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outdex = outdex + 1;
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end
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end
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// decryption tests
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outdex = 0;
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while (outdex < 19) begin
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@(posedge clk)
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if (validout) begin
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// detected an error -> print error message
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// increment error counter
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if (dataout != test_data[outdex]) begin
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$display ("error, output was %h - should have been %h", dataout, test_data[outdex]);
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errors = errors + 1;
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end
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outdex = outdex + 1;
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end
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end
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if (errors) begin
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$display ("simulation finished, %0d errors detected :(", errors);
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end else begin
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$display ("simulation tests finished, no errors detected :)");
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end
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$display ("#############");
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@(posedge clk)
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$finish;
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end
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// dut
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tdes i_tdes (
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.reset_i(reset),
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.clk_i(clk),
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.mode_i(mode),
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.key1_i(key1),
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.key2_i(key2),
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.key3_i(key3),
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.data_i(datain),
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.valid_i(validin),
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.data_o(dataout),
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.valid_o(validout),
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.ready_o(ready)
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);
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endmodule
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