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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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198
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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cc268c2efb
master
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cryptocores
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aes
/
rtl
/
vhdl
History
T. Meissner
c5a7007ac5
Implement key schedule for AES decryption, unoptimized
4 years ago
..
aes.vhd
First working version of AES enc & dec
6 years ago
aes_dec.vhd
Implement key schedule for AES decryption, unoptimized
4 years ago
aes_enc.vhd
Make PSL compatible with simulation & synthesis
4 years ago
aes_pkg.vhd
Implement key schedule for AES decryption, unoptimized
4 years ago