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91 lines
2.5 KiB
91 lines
2.5 KiB
-- ======================================================================
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-- AES encryption/decryption testbench
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-- tests according to NIST special publication
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-- Copyright (C) 2011 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- ======================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.env.all;
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use work.aes_pkg.all;
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entity tb_aes is
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end entity tb_aes;
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architecture rtl of tb_aes is
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signal s_reset : std_logic := '0';
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signal s_clk : std_logic := '0';
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signal s_mode : std_logic := '0';
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signal s_key : std_logic_vector(0 to 127) := (others => '0');
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signal s_datain : std_logic_vector(0 to 127) := (others => '0');
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signal s_validin : std_logic := '0';
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signal s_acceptout : std_logic;
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signal s_dataout : std_logic_vector(0 to 127);
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signal s_validout : std_logic;
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signal s_acceptin : std_logic;
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component aes is
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port (
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reset_i : in std_logic;
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clk_i : in std_logic;
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mode_i : in std_logic;
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key_i : in std_logic_vector(0 TO 127);
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data_i : in std_logic_vector(0 TO 127);
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valid_i : in std_logic;
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accept_o : out std_logic;
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data_o : out std_logic_vector(0 TO 127);
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valid_o : out std_logic;
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accept_i : in std_logic
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);
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end component aes;
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begin
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s_clk <= not(s_clk) after 10 ns;
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s_reset <= '1' after 100 ns;
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i_aes : aes
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port map (
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reset_i => s_reset,
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clk_i => s_clk,
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mode_i => s_mode,
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key_i => s_key,
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data_i => s_datain,
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valid_i => s_validin,
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accept_o => s_acceptout,
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data_o => s_dataout,
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valid_o => s_validout,
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accept_i => s_acceptin
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);
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end architecture rtl;
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