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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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143
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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cryptocores
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History
T. Meissner
dafb56c966
added wait for disactivated reset before running testcases
11 years ago
..
rtl
moved array type definitions out of functions to head of package, instances now also in package head and are constants
11 years ago
sim
added wait for disactivated reset before running testcases
11 years ago