-- ======================================================================
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-- DES encryption/decryption
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-- algorithm according to FIPS 46-3 specification
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-- Copyright (C) 2011 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- ======================================================================
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-- Revision 1.0 2011/09/17
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-- Initial release
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.ALL;
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entity tb_des is
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end entity tb_des;
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architecture rtl of tb_des is
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signal s_clk : std_logic : := '0';
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signal s_des1_key : std_logic_vector(0 to 63);
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signal s_des1_datain : std_logic_vector(0 to 63);
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signal s_des1_validin : std_logic;
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signal s_des1_dataout : std_logic_vector(0 to 63);
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signal s_des1_validout : std_logic;
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signal s_des2_key : std_logic_vector(0 to 63);
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signal s_des2_dataout : std_logic_vector(0 to 63);
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signal s_des2_validout : std_logic;
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component des is
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port (
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clk_i : IN std_logic;
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mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
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key_i : IN std_logic_vector(0 TO 63);
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data_i : IN std_logic_vector(0 TO 63);
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valid_i : IN std_logic;
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data_o : OUT std_logic_vector(0 TO 63);
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valid_o : OUT std_logic
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);
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end component des;
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begin
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s_clk <= not(s_clk) after 10 ns;
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testinputP : process is
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begin
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for index in 0 to 31 loop
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wait until s_clk = '1';
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s_valid <= '1';
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s_mode
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end process testinputP;
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testoutputP : process is
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begin
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wait until s_clk = '1';
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end process testoutputP;
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i1_des : des
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port map (
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clk_i => s_clk,
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mode_i => '0',
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key_i => s_des1_key,
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data_i => s_des1_datain,
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valid_i => s_des1_validin,
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data_o => s_des1_dataout,
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valid_o => s_des1_validout
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);
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i2_des : des
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port map (
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clk_i => s_clk,
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mode_i => '1',
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key_i => s_des2_key,
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data_i => s_des1_dataout,
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valid_i => s_des1_validout,
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data_o => s_des2_dataout,
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valid_o => s_des2_validout
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);
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end architecture rtl;
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