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177 lines
5.5 KiB
177 lines
5.5 KiB
-- ======================================================================
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-- TDES encryption/decryption testbench
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-- tests according to NIST 800-17 special publication
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-- Copyright (C) 2011 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- ======================================================================
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-- Revision 0.1 2011/10/08
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-- Initial release
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tb_tdes is
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end entity tb_tdes;
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architecture rtl of tb_tdes is
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type t_array is array (natural range <>) of std_logic_vector(0 to 63);
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constant c_table_test_plain : t_array(0 to 18) :=
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(x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172",
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x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A",
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x"0756D8E0774761D2", x"762514B829BF486A", x"3BDD119049372802",
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x"26955F6835AF609A", x"164D5E404F275232", x"6B056E18759F5CCA",
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x"004BD6EF09176062", x"480D39006EE762F2", x"437540C8698F3CFA",
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x"072D43A077075292", x"02FE55778117F12A", x"1D9D5C5018F728C2",
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x"305532286D6F295A");
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signal s_tdes_answers : t_array(0 to 19);
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signal s_reset : std_logic := '0';
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signal s_clk : std_logic := '0';
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signal s_mode : std_logic := '0';
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signal s_key1 : std_logic_vector(0 to 63) := (others => '0');
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signal s_key2 : std_logic_vector(0 to 63) := (others => '0');
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signal s_key3 : std_logic_vector(0 to 63) := (others => '0');
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signal s_datain : std_logic_vector(0 to 63) := (others => '0');
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signal s_validin : std_logic := '0';
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signal s_ready : std_logic := '0';
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signal s_dataout : std_logic_vector(0 to 63);
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signal s_validout : std_logic;
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component tdes is
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port (
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reset_i : in std_logic;
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clk_i : in std_logic;
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mode_i : in std_logic;
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key1_i : in std_logic_vector(0 to 63);
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key2_i : in std_logic_vector(0 TO 63);
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key3_i : in std_logic_vector(0 TO 63);
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data_i : in std_logic_vector(0 TO 63);
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valid_i : in std_logic;
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data_o : out std_logic_vector(0 TO 63);
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valid_o : out std_logic;
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ready_o : out std_logic
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);
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end component tdes;
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begin
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s_reset <= '1' after 100 ns;
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s_clk <= not(s_clk) after 10 ns;
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teststimuliP : process is
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begin
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s_mode <= '0';
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s_validin <= '0';
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s_key1 <= (others => '0');
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s_key2 <= (others => '0');
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s_key3 <= (others => '0');
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s_datain <= (others => '0');
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-- ENCRYPTION TESTS
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-- cbc known answers test
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for index in c_table_test_plain'range loop
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wait until rising_edge(s_clk) and s_ready = '1';
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s_key1 <= x"1111111111111111";
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s_key2 <= x"5555555555555555";
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s_key3 <= x"9999999999999999";
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s_validin <= '1';
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s_datain <= c_table_test_plain(index);
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wait until rising_edge(s_clk);
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s_validin <= '0';
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end loop;
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wait until rising_edge(s_clk);
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s_mode <= '0';
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s_validin <= '0';
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s_key1 <= (others => '0');
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s_key2 <= (others => '0');
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s_key3 <= (others => '0');
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s_datain <= (others => '0');
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wait for 1 us;
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-- DECRYPTION TESTS
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-- cbc known answer test
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for index in c_table_test_plain'range loop
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wait until rising_edge(s_clk) and s_ready = '1';
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s_key1 <= x"1111111111111111";
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s_key2 <= x"5555555555555555";
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s_key3 <= x"9999999999999999";
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s_mode <= '1';
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s_validin <= '1';
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s_datain <= s_tdes_answers(index);
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wait until rising_edge(s_clk);
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s_validin <= '0';
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s_mode <= '0';
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end loop;
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wait until rising_edge(s_clk);
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s_mode <= '0';
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s_validin <= '0';
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s_key1 <= (others => '0');
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s_key2 <= (others => '0');
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s_key3 <= (others => '0');
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s_datain <= (others => '0');
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wait;
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end process teststimuliP;
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testcheckerP : process is
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begin
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report "# ENCRYPTION TESTS";
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for index in c_table_test_plain'range loop
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wait until rising_edge(s_clk) and s_validout = '1';
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s_tdes_answers(index) <= s_dataout;
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end loop;
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report "# DECRYPTION TESTS";
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report "# tdes known answer test";
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for index in c_table_test_plain'range loop
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wait until rising_edge(s_clk) and s_validout = '1';
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assert (s_dataout = c_table_test_plain(index))
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report "decryption error"
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severity error;
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end loop;
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report "# Successfully passed all tests";
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wait;
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end process testcheckerP;
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i_tdes : tdes
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port map (
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reset_i => s_reset,
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clk_i => s_clk,
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mode_i => s_mode,
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key1_i => s_key1,
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key2_i => s_key2,
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key3_i => s_key3,
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data_i => s_datain,
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valid_i => s_validin,
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data_o => s_dataout,
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valid_o => s_validout,
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ready_o => s_ready
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);
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end architecture rtl;
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