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138 lines
4.6 KiB
138 lines
4.6 KiB
-- ======================================================================
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-- CBC-DES encryption/decryption
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-- algorithm according to FIPS 46-3 specification
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-- Copyright (C) 2007 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- ======================================================================
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-- Revision 0.1 2011/09/23
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-- Initial release, incomplete and may contain bugs
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.des_pkg.all;
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entity cbcdes is
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port (
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reset_i : in std_logic; -- low active async reset
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clk_i : in std_logic; -- clock
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start_i : in std_logic; -- start cbc
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mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
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key_i : in std_logic_vector(0 TO 63); -- key input
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iv_i : in std_logic_vector(0 to 63); -- iv input
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data_i : in std_logic_vector(0 TO 63); -- data input
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valid_i : in std_logic; -- input key/data valid flag
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ready_o : out std_logic; -- ready to encrypt/decrypt
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data_o : out std_logic_vector(0 TO 63); -- data output
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valid_o : out std_logic -- output data valid flag
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);
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end entity cbcdes;
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architecture rtl of cbcdes is
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component des is
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port (
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clk_i : IN std_logic; -- clock
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mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
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key_i : IN std_logic_vector(0 TO 63); -- key input
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data_i : IN std_logic_vector(0 TO 63); -- data input
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valid_i : IN std_logic; -- input key/data valid flag
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data_o : OUT std_logic_vector(0 TO 63); -- data output
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valid_o : OUT std_logic -- output data valid flag
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);
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end component des;
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signal s_mode : std_logic;
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signal s_start : std_logic;
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signal s_iv : std_logic_vector(0 to 63);
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signal s_datain : std_logic_vector(0 to 63);
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signal s_des_datain : std_logic_vector(0 to 63);
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signal s_validin : std_logic;
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signal s_dataout : std_logic_vector(0 to 63);
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signal s_validout : std_logic;
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signal s_ready : std_logic;
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signal s_reset : std_logic;
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begin
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s_des_datain <= iv_i xor data_i when mode_i = '0' and start_i = '1' else
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s_dataout xor data_i when mode_i = '0' and start_i = '0' else
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data_i;
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data_o <= s_iv xor s_dataout when s_mode = '1' and s_start = '1' else
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s_datain xor s_dataout when s_mode = '1' and s_start = '0' else
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s_dataout;
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ready_o <= s_ready;
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s_validin <= valid_i and s_ready;
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valid_o <= s_validout;
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inputregister : process(clk_i, reset_i) is
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begin
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if(reset_i = '0') then
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s_reset <= '0';
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s_mode <= '0';
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s_start <= '0';
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s_iv <= (others => '0');
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s_datain <= (others => '0');
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elsif(rising_edge(clk_i)) then
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s_reset <= reset_i;
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if(valid_i = '1' and s_ready = '1') then
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s_mode <= mode_i;
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s_start <= start_i;
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s_iv <= iv_i;
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s_datain <= data_i;
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end if;
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end if;
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end process inputregister;
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outputregister : process(clk_i, reset_i) is
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begin
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if(reset_i = '0') then
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s_ready <= '0';
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elsif(rising_edge(clk_i)) then
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if(valid_i = '1' and s_ready = '1') then
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s_ready <= '0';
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end if;
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if(s_validout = '1' or (reset_i = '1' and s_reset = '0')) then
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s_ready <= '1';
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end if;
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end if;
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end process outputregister;
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i_des : des
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port map (
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clk_i => clk_i,
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mode_i => mode_i,
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key_i => key_i,
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data_i => s_des_datain,
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valid_i => s_validin,
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data_o => s_dataout,
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valid_o => s_validout
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);
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end architecture rtl;
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