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cryptocores
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cryptography ip-cores in vhdl / verilog
27 Commits
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1.7 MiB
 
 
 
 
 
Tree: f0cba7ebb6
cryptocores/cbcdes
Torsten Meissner f0cba7ebb6 expanded simulation time to 220us 14 years ago
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rtl register mode_i and iv_i only if start_i is high 14 years ago
sim expanded simulation time to 220us 14 years ago