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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/counter/Makefile

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parameterize design; fix minor makefile problemswq
6 years ago
​
Add counter as example for initial reset problems
6 years ago
​
parameterize design; fix minor makefile problemswq
6 years ago
Add counter as example for initial reset problems
6 years ago
​
 
  1. .PHONY: counter
  2. counter: counter.vhd counter_t.sv counter_f.sby
  3. 	sby -f -d work counter_f.sby
  4. 

  5. .PHONY: clean
  6. clean:
  7. 	rm -rf work