Trying to verify Verilog/VHDL designs with formal methods and tools
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

7 lines
129 B

  1. .PHONY: counter
  2. counter: counter.vhd counter_t.sv counter_f.sby
  3. sby -f -d work counter_f.sby
  4. .PHONY: clean
  5. clean:
  6. rm -rf work