Trying to verify Verilog/VHDL designs with formal methods and tools
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T. Meissner 36d6da1943 Minor updates to README file 2 years ago
alu Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 4 years ago
counter Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 4 years ago
dlatchsr Add example for dlatchsr error 4 years ago
vai_reg Add png versions of read/write waveform examples 3 years ago
.gitignore Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv 4 years ago
LICENSE.md Inital commit 4 years ago
README.md Minor updates to README file 2 years ago

README.md

The original repository is located on my own git-server at https://git.goodcleanfun.de/tmeissner/formal_hw_verification

It is mirrored to github with every push, so both should be in sync.

formal_hw_verification

Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with SymbiYosys, a front-end for formal verification flows based on Yosys. Some examples use the VHDL/SystemVerilog frontend plugin by Verific which isn't free SW and not included in the free Yosys version. See on the Symbiotic EDA website for more information.

There is a branch named ghdl-synth which uses ghdlsynth-beta as VHDL frontend plugin for SymbiYosys. Furthermore using GHDL(synth) as synthesis frontend allows using PSL as verification language. Only the vai_reg design can be verified in this branch at the moment.

alu

A simple ALU design in VHDL. The formal checks contain various simple properties used by assert & cover directives which are proved with the SymbiYosys tool.

counter

A simple counter design in VHDL. The testbench contains various simple properties used by assert & cover directives which are proved with the SymbiYosys tool.

dlatch

A simple test design which generates the Unsupported cell type $dlatchsr error using with Verific plugin.

vai_reg

A simple register file with VAI (valid-accept-interface) which serves as test design to try formal verification of FSMs.