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T. Meissner 5 months ago
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      LICENSE.md
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+work/*

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LICENSE.md View File

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+#GNU LESSER GENERAL PUBLIC LICENSE
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+Version 3, 29 June 2007
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+
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+
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+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
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+ Everyone is permitted to copy and distribute verbatim copies
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+ of this license document, but changing it is not allowed.
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+
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+
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+  This version of the GNU Lesser General Public License incorporates
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+the terms and conditions of version 3 of the GNU General Public
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+License, supplemented by the additional permissions listed below.
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+
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+#### 0. Additional Definitions.
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+
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+  As used herein, "this License" refers to version 3 of the GNU Lesser
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+General Public License, and the "GNU GPL" refers to version 3 of the GNU
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+General Public License.
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+  "The Library" refers to a covered work governed by this License,
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+other than an Application or a Combined Work as defined below.
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+  An "Application" is any work that makes use of an interface provided
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+#### 1. Exception to Section 3 of the GNU GPL.
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+  You may convey a covered work under sections 3 and 4 of this License
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+#### 2. Conveying Modified Versions.
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+   for conveying Corresponding Source.)
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+#### 5. Combined Libraries.
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+  You may place library facilities that are a work based on the
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+   accompanying uncombined form of the same work.
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+#### 6. Revised Versions of the GNU Lesser General Public License.
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+  The Free Software Foundation may publish revised and/or new versions
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+of the GNU Lesser General Public License from time to time. Such new
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+differ in detail to address new problems or concerns.
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+
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+  Each version is given a distinguishing version number. If the
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+Library as you received it specifies that a certain numbered version
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+of the GNU Lesser General Public License "or any later version"
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+applies to it, you have the option of following the terms and
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+conditions either of that published version or of any later version
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+published by the Free Software Foundation. If the Library as you
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+received it does not specify a version number of the GNU Lesser
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+General Public License, you may choose any version of the GNU Lesser
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+General Public License ever published by the Free Software Foundation.
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+  If the Library as you received it specifies that a proxy can decide
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+Library.

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+# formal_verification
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+
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+Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with SymbiYosys, a free formal verification tool based on Yosys. Some examples use the VHDL/SystemVerilog parser plugin by Verific which isn't free SW and nit included in the free Yosys version. See on the [Symbiotic EDA website](https://www.symbioticeda.com) for more information. 
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+
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+### alu
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+A simple ALU design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple properties for assert & cover directives which are proved with the SymbiYosys tool.

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+*/work/*

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+alu: alu.vhd alu_t.v alu_f.sby
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+	sby -f -d work alu_f.sby

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+library ieee;
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+use ieee.std_logic_1164.all;
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+use ieee.numeric_std.all;
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+
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+
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+
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+entity alu is
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+  port (
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+    Reset_n_i  : in  std_logic;
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+    Clk_i      : in  std_logic;
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+    Opc_i      : in  std_logic_vector(1 downto 0);
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+    DinA_i     : in  std_logic_vector(31 downto 0);
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+    DinB_i     : in  std_logic_vector(31 downto 0);
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+    Dout_o     : out std_logic_vector(31 downto 0);
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+    OverFlow_o : out std_logic
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+  );
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+end entity alu;
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+
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+
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+
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+architecture rtl of alu is
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+
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+
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+  constant c_add : std_logic_vector(1 downto 0) := "00";
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+  constant c_sub : std_logic_vector(1 downto 0) := "01";
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+  constant c_and : std_logic_vector(1 downto 0) := "10";
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+  constant c_or  : std_logic_vector(1 downto 0) := "11";
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+
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+
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+begin
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+
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+
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+  process (Reset_n_i, Clk_i) is
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+  begin
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+    if (Reset_n_i = '0') then
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+      Dout_o <= (others => '0');
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+    elsif (rising_edge(Clk_i)) then
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+      case Opc_i is
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+        when c_add => (OverFlow_o, Dout_o) <=
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+	  std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) +
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+	                   resize(unsigned(DinB_i), Dout_o'length+1));
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+        when c_sub => (OverFlow_o, Dout_o) <=
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+	  std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) -
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+	                   resize(unsigned(DinB_i), Dout_o'length+1));
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+	when c_and => Dout_o <= DinA_i and DinB_i;
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+	when c_or  => Dout_o <= DinA_i or DinB_i;
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+	when others => null;
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+      end case;
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+    end if;
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+  end process;
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+
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+
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+end architecture rtl;
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+

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+[options]
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+mode prove
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+#mode bmc
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+#depth 20
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+
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+[engines]
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+smtbmc
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+
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+[script]
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+verific -vhdl alu.vhd
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+verific -formal alu_t.sv
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+prep -top alu_t
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+
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+[files]
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+alu.vhd
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+alu_t.sv

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+module alu_t (
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+    inout        Reset_n_i,
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+    input        Clk_i,
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+    input  [1:0] Opc_i,
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+    input  [31:0] DinA_i,
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+    input  [31:0] DinB_i,
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+    output [31:0] Dout_o,
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+    output       OverFlow_o
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+);
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+
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+
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+  alu alu_i (
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+    .Reset_n_i(Reset_n_i),
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+    .Clk_i(Clk_i),
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+    .Opc_i(Opc_i),
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+    .DinA_i(DinA_i),
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+    .DinB_i(DinB_i),
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+    .Dout_o(Dout_o),
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+    .OverFlow_o(OverFlow_o)
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+  );
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+
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+  const logic [1:0] OPC_ADD = 0;
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+  const logic [1:0] OPC_SUB = 1;
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+  const logic [1:0] OPC_AND = 2;
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+  const logic [1:0] OPC_OR  = 3;
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+
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+  initial begin
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+    assume (!Reset_n_i);
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+  end
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+
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+  bit unsigned [32:0] dina, dinb;
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+
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+  assign dina = DinA_i;
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+  assign dinb = DinB_i;
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+
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+  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_ADD |=> Dout_o == ($past(DinA_i) + $past(DinB_i)));
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+  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_ADD && (dina + dinb) > 2**32-1 |=> OverFlow_o);
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+  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_SUB |=> Dout_o == ($past(DinA_i) - $past(DinB_i)));
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+  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_SUB && (dina - dinb) > 2**32-1 |=> OverFlow_o);
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+  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_AND |=> Dout_o == ($past(DinA_i) & $past(DinB_i)));
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+  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_OR |=> Dout_o == ($past(DinA_i) | $past(DinB_i)));
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+
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+  assert property (@(posedge Clk_i or negedge Clk_i) !Reset_n_i |-> Dout_o == 0);
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+
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+  property cover_opc (opc);
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+    @(posedge Clk_i)
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+      disable iff (!Reset_n_i) Opc_i == opc;
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+  endproperty
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+
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+  cover property (cover_opc(OPC_ADD));
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+  cover property (cover_opc(OPC_SUB));
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+  cover property (cover_opc(OPC_AND));
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+  cover property (cover_opc(OPC_OR));
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+
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+
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+endmodule
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+