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verific_problem
T. Meissner 3 years ago
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work/*

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#GNU LESSER GENERAL PUBLIC LICENSE
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# formal_verification
Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with SymbiYosys, a free formal verification tool based on Yosys. Some examples use the VHDL/SystemVerilog parser plugin by Verific which isn't free SW and nit included in the free Yosys version. See on the [Symbiotic EDA website](https://www.symbioticeda.com) for more information.
### alu
A simple ALU design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple properties for assert & cover directives which are proved with the SymbiYosys tool.

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alu: alu.vhd alu_t.v alu_f.sby
sby -f -d work alu_f.sby

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Opc_i : in std_logic_vector(1 downto 0);
DinA_i : in std_logic_vector(31 downto 0);
DinB_i : in std_logic_vector(31 downto 0);
Dout_o : out std_logic_vector(31 downto 0);
OverFlow_o : out std_logic
);
end entity alu;
architecture rtl of alu is
constant c_add : std_logic_vector(1 downto 0) := "00";
constant c_sub : std_logic_vector(1 downto 0) := "01";
constant c_and : std_logic_vector(1 downto 0) := "10";
constant c_or : std_logic_vector(1 downto 0) := "11";
begin
process (Reset_n_i, Clk_i) is
begin
if (Reset_n_i = '0') then
Dout_o <= (others => '0');
elsif (rising_edge(Clk_i)) then
case Opc_i is
when c_add => (OverFlow_o, Dout_o) <=
std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) +
resize(unsigned(DinB_i), Dout_o'length+1));
when c_sub => (OverFlow_o, Dout_o) <=
std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) -
resize(unsigned(DinB_i), Dout_o'length+1));
when c_and => Dout_o <= DinA_i and DinB_i;
when c_or => Dout_o <= DinA_i or DinB_i;
when others => null;
end case;
end if;
end process;
end architecture rtl;

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[options]
mode prove
#mode bmc
#depth 20
[engines]
smtbmc
[script]
verific -vhdl alu.vhd
verific -formal alu_t.sv
prep -top alu_t
[files]
alu.vhd
alu_t.sv

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module alu_t (
inout Reset_n_i,
input Clk_i,
input [1:0] Opc_i,
input [31:0] DinA_i,
input [31:0] DinB_i,
output [31:0] Dout_o,
output OverFlow_o
);
alu alu_i (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Opc_i(Opc_i),
.DinA_i(DinA_i),
.DinB_i(DinB_i),
.Dout_o(Dout_o),
.OverFlow_o(OverFlow_o)
);
const logic [1:0] OPC_ADD = 0;
const logic [1:0] OPC_SUB = 1;
const logic [1:0] OPC_AND = 2;
const logic [1:0] OPC_OR = 3;
initial begin
assume (!Reset_n_i);
end
bit unsigned [32:0] dina, dinb;
assign dina = DinA_i;
assign dinb = DinB_i;
assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_ADD |=> Dout_o == ($past(DinA_i) + $past(DinB_i)));
assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_ADD && (dina + dinb) > 2**32-1 |=> OverFlow_o);
assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_SUB |=> Dout_o == ($past(DinA_i) - $past(DinB_i)));
assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_SUB && (dina - dinb) > 2**32-1 |=> OverFlow_o);
assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_AND |=> Dout_o == ($past(DinA_i) & $past(DinB_i)));
assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == OPC_OR |=> Dout_o == ($past(DinA_i) | $past(DinB_i)));
assert property (@(posedge Clk_i or negedge Clk_i) !Reset_n_i |-> Dout_o == 0);
property cover_opc (opc);
@(posedge Clk_i)
disable iff (!Reset_n_i) Opc_i == opc;
endproperty
cover property (cover_opc(OPC_ADD));
cover property (cover_opc(OPC_SUB));
cover property (cover_opc(OPC_AND));
cover property (cover_opc(OPC_OR));
endmodule

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