Trying to verify Verilog/VHDL designs with formal methods and tools
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T. Meissner 4feec0fff6 Inital commit 4 years ago
alu Inital commit 4 years ago
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LICENSE.md Inital commit 4 years ago
README.md Inital commit 4 years ago

README.md

formal_verification

Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with SymbiYosys, a free formal verification tool based on Yosys. Some examples use the VHDL/SystemVerilog parser plugin by Verific which isn't free SW and nit included in the free Yosys version. See on the Symbiotic EDA website for more information.

alu

A simple ALU design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple properties for assert & cover directives which are proved with the SymbiYosys tool.