Trying to verify Verilog/VHDL designs with formal methods and tools
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 

16 lines
158 B

[options]
mode prove
#mode bmc
#depth 20
[engines]
smtbmc
[script]
verific -vhdl alu.vhd
verific -formal alu_t.sv
prep -top alu_t
[files]
alu.vhd
alu_t.sv