tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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Add simple VAI register file as base to try to formal verify FSM designs

6 years ago

[options]
depth 30
wait on
mode prove
#mode bmc

[engines]
smtbmc
#abc pdr

[script]
verific -vhdl vai_reg.vhd
verific -formal properties.sv
verific -import -extnets -all vai_reg
prep -top vai_reg

[files]
vai_reg.vhd
properties.sv