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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/vai_reg
T. Meissner 1deb6e9789 Add vai_reg to README; using SVA default clocking 5 years ago
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Makefile Add simple VAI register file as base to try to formal verify FSM designs 5 years ago
properties.sv Add vai_reg to README; using SVA default clocking 5 years ago
symbiyosys.sby Add simple VAI register file as base to try to formal verify FSM designs 5 years ago
vai_reg.vhd Add DoutValid_o to condition for state change in putput states 5 years ago