tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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Making alu design work with GHDL synthesis * Remove unused SVA properties file * Makefile optimizations * Use prep auto-top option to prevent error with not founded top-level module * Rewrite assignments of Dout_o & Overflow_o as GHDL synthesis don't support concatenation on left side of assignments * Add some simple PSL assertions

5 years ago

Add alu checks * Add asserts for correct behaviour of Overflow flag * Switch to smtbmc engine in prove mode (much faster than abc)

5 years ago

Making alu design work with GHDL synthesis * Remove unused SVA properties file * Makefile optimizations * Use prep auto-top option to prevent error with not founded top-level module * Rewrite assignments of Dout_o & Overflow_o as GHDL synthesis don't support concatenation on left side of assignments * Add some simple PSL assertions

5 years ago

Add alu checks * Add asserts for correct behaviour of Overflow flag * Switch to smtbmc engine in prove mode (much faster than abc)

5 years ago

Making alu design work with GHDL synthesis * Remove unused SVA properties file * Makefile optimizations * Use prep auto-top option to prevent error with not founded top-level module * Rewrite assignments of Dout_o & Overflow_o as GHDL synthesis don't support concatenation on left side of assignments * Add some simple PSL assertions

5 years ago

[tasks]
cover
bmc
prove

[options]
depth 25
cover: mode cover
bmc: mode bmc
prove: mode prove

[engines]
cover: smtbmc z3
bmc: abc bmc3
prove: smtbmc z3

[script]
ghdl --std=08 -gWidth=16 -gFormal=true alu.vhd -e alu
prep -auto-top

[files]
alu.vhd