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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/vai_reg/trace.gtkw

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Add some more signals to trace
6 years ago
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Fix req cai handling; add more properties
6 years ago
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Add some more signals to trace
6 years ago
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Fix req cai handling; add more properties
6 years ago
Add some more signals to trace
6 years ago
 
  1. smt_step
  2. -Global
  3. vai_reg.Reset_n_i
  4. vai_reg.properties.Clk_i
  5. -VAI req
  6. vai_reg.properties.DinStart_i
  7. vai_reg.properties.DinStop_i
  8. vai_reg.properties.Din_i[7:0]
  9. vai_reg.properties.DinValid_i
  10. vai_reg.properties.DinAccept_o
  11. -VAI ack
  12. vai_reg.properties.DoutStart_o
  13. vai_reg.properties.DoutStop_o
  14. vai_reg.properties.Dout_o[7:0]
  15. vai_reg.properties.DoutValid_o
  16. vai_reg.properties.DoutAccept_i
  17. -Internal
  18. vai_reg.properties.s_fsm_state[2:0]
  19. vai_reg.properties.s_header[7:0]
  20. vai_reg.properties.s_data[7:0]
  21. vai_reg.properties.s_register[63:0]
  22. vai_reg.properties.s_error