Trying to verify Verilog/VHDL designs with formal methods and tools
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22 lines
556 B

smt_step
-Global
vai_reg.Reset_n_i
vai_reg.properties.Clk_i
-VAI req
vai_reg.properties.DinStart_i
vai_reg.properties.DinStop_i
vai_reg.properties.Din_i[7:0]
vai_reg.properties.DinValid_i
vai_reg.properties.DinAccept_o
-VAI ack
vai_reg.properties.DoutStart_o
vai_reg.properties.DoutStop_o
vai_reg.properties.Dout_o[7:0]
vai_reg.properties.DoutValid_o
vai_reg.properties.DoutAccept_i
-Internal
vai_reg.properties.s_fsm_state[2:0]
vai_reg.properties.s_header[7:0]
vai_reg.properties.s_data[7:0]
vai_reg.properties.s_register[63:0]
vai_reg.properties.s_error