formal_hw_verification/vai_fifo/Makefile

DUT := vai_fifo
SRC := ../fifo/fifo.vhd ../fwft_fifo/fwft_fifo.vhd ${DUT}.vhd

.PHONY: cover bmc prove synth all clean

all: cover bmc prove

cover bmc prove: ${DUT}.vhd symbiyosys.sby
	sby --yosys "yosys -m ghdl" -f -d work/${DUT}-$@ symbiyosys.sby $@

${DUT}_synth.vhd: ${SRC}
	ghdl --synth --std=08 --no-formal -gDepth=16 -gWidth=16 ${SRC} -e ${DUT} > $@

synth: ${DUT}.json
${DUT}.json: ${DUT}_synth.vhd
	yosys -m ghdl -p 'ghdl --std=08 --no-formal -gDepth=16 -gWidth=16 ${SRC} -e ${DUT}; synth_ice40 -top ${DUT} -json $@'

clean:
	rm -rf work ${DUT}.json ${DUT}_synth.vhd