formal_hw_verification

Trying to verify Verilog/VHDL designs with formal methods and tools

History

T. Meissner 4a58b1789c fifo: Add example for GHDL property replication * By replacing the goto operator with non-literal parameter by counting the read enabled with simple VHDL counters we can now replicate the properties instead of writing them all out. * Decrease the data width to decrease run-time of unbounded proofs		3 years ago
..
Makefile	Add fwft-fifo & use that for vai-fifo; minor fixes	4 years ago
symbiyosys.sby	fifo: Add example for GHDL property replication	3 years ago
vai_fifo.vhd	Add fwft-fifo & use that for vai-fifo; minor fixes	4 years ago