tmeissner
/
formal_hw_verification
1
0
Fork 0
Code Issues 0 Pull Requests 0 Releases 6 Wiki Activity
Trying to verify Verilog/VHDL designs with formal methods and tools
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
11 Commits
3 Branches
324 KiB
Tree: 5b8d9650e0
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '5b8d9650e0'
${ noResults }
formal_hw_verification/counter/counter_f.sby

18 lines
197 B
Raw Normal View History

Add counter as example for initial reset problems
6 years ago
​
Add genric setting counter end value
6 years ago
Add counter as example for initial reset problems
6 years ago
Add genric setting counter end value
6 years ago
Add counter as example for initial reset problems
6 years ago
​
Add genric setting counter end value
6 years ago
Make the unbounded prove work * Fixed bug in check for end value in counter unit ;) * Use abc engine with pdr solver * Add asserts for reset
6 years ago
Add counter as example for initial reset problems
6 years ago
​
​
​
​
​
​
​
​
 
  1. [options]
  2. mode prove
  3. depth 30
  4. multiclock on
  5. wait on
  6. 

  7. [engines]
  8. smtbmc
  9. abc pdr
  10. 

  11. [script]
  12. verific -vhdl counter.vhd
  13. verific -formal counter_t.sv
  14. prep -top counter_t
  15. 

  16. [files]
  17. counter.vhd
  18. counter_t.sv