Trying to verify Verilog/VHDL designs with formal methods and tools
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18 lines
197 B

[options]
mode prove
depth 30
multiclock on
wait on
[engines]
smtbmc
abc pdr
[script]
verific -vhdl counter.vhd
verific -formal counter_t.sv
prep -top counter_t
[files]
counter.vhd
counter_t.sv