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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/counter/counter_f.sby

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Add counter as example for initial reset problems
6 years ago
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Add genric setting counter end value
6 years ago
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Add counter as example for initial reset problems
6 years ago
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Add genric setting counter end value
6 years ago
Make the unbounded prove work * Fixed bug in check for end value in counter unit ;) * Use abc engine with pdr solver * Add asserts for reset
6 years ago
Add counter as example for initial reset problems
6 years ago
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  1. [options]
  2. mode prove
  3. depth 30
  4. wait on
  5. 

  6. [engines]
  7. smtbmc
  8. abc pdr
  9. 

  10. [script]
  11. verific -vhdl counter.vhd
  12. verific -formal counter_t.sv
  13. prep -top counter_t
  14. 

  15. [files]
  16. counter.vhd
  17. counter_t.sv