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formal_hw_verification
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19 Commits (60e2c0f301870db303db5c260117888dad9d7c43)
 

Author SHA1 Message Date
  T. Meissner 60e2c0f301 Add some more signals to trace 6 years ago
  T. Meissner b48e99c1f0 Simplify signal generation 6 years ago
  T. Meissner 4e30f44cb0 Fix req cai handling; add more properties 6 years ago
  T. Meissner 1deb6e9789 Add vai_reg to README; using SVA default clocking 6 years ago
  T. Meissner 63fc34f66a Add DoutValid_o to condition for state change in putput states 6 years ago
  T. Meissner a0f6a0b81d Add simple VAI register file as base to try to formal verify FSM designs 6 years ago
  T. Meissner 307c6b5f44 Add clock constrain using global clocking 6 years ago
  T. Meissner 7aa4aa52a8 Data in/put width now unconstrained 6 years ago
  T. Meissner 5b8d9650e0 Add genric setting counter end value 6 years ago
  T. Meissner 6d230226f2 Add info about git repo 6 years ago
  T. Meissner 12e20b1da2 Some small improvements 6 years ago
  T. Meissner 9d03113704 Make the unbounded prove work 6 years ago
  T. Meissner 445c013e5c Add example for dlatchsr error 6 years ago
  T. Meissner 3c042a168b Remove unused Data_i port from testbench 6 years ago
  T. Meissner dd0642e762 parameterize design; fix minor makefile problemswq 6 years ago
  T. Meissner 9d0198b0b4 Add counter as example for initial reset problems 6 years ago
  T. Meissner fca663d7ac Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv 6 years ago
  T. Meissner 2f7959db61 Remove gitignore from alu folder; added link to Yosys 6 years ago
  T. Meissner 4feec0fff6 Inital commit 6 years ago