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Simplify signal generation

T. Meissner 7 months ago
parent
commit
b48e99c1f0
1 changed files with 1 additions and 2 deletions
  1. 1
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      vai_reg/vai_reg.vhd

+ 1
- 2
vai_reg/vai_reg.vhd View File

@@ -50,8 +50,7 @@ architecture rtl of vai_reg is
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 begin
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-  s_dout_accepted <= true when DoutValid_o = '1' and DoutAccept_i = '1' else
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-                     false;
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+  s_dout_accepted <= (DoutValid_o and DoutAccept_i) = '1';
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   process (Reset_n_i, Clk_i) is