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formal_hw_verification
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Simplify signal generation

verific
T. Meissner 6 years ago
parent
4e30f44cb0
commit
b48e99c1f0
1 changed files with 1 additions and 2 deletions
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    -2
      vai_reg/vai_reg.vhd

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@ -50,8 +50,7 @@ architecture rtl of vai_reg is
begin
s_dout_accepted <= true when DoutValid_o = '1' and DoutAccept_i = '1' else
false;
s_dout_accepted <= (DoutValid_o and DoutAccept_i) = '1';
process (Reset_n_i, Clk_i) is


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