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Remove gitignore from alu folder; added link to Yosys

verific_problem
T. Meissner 3 years ago
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      README.md
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      alu/.gitignore
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README.md View File

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# formal_verification
Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with SymbiYosys, a free formal verification tool based on Yosys. Some examples use the VHDL/SystemVerilog parser plugin by Verific which isn't free SW and nit included in the free Yosys version. See on the [Symbiotic EDA website](https://www.symbioticeda.com) for more information.
Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with SymbiYosys, a front-end for formal verification flows based on [Yosys](https://github.com/YosysHQ). Some examples use the VHDL/SystemVerilog parser plugin by Verific which isn't free SW and not included in the free Yosys version. See on the [Symbiotic EDA website](https://www.symbioticeda.com) for more information.
### alu
A simple ALU design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple properties for assert & cover directives which are proved with the SymbiYosys tool.
A simple ALU design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple SVA properties used by assert & cover directives which are proved with the SymbiYosys tool.

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*/work/*

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alu/Makefile View File

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alu: alu.vhd alu_t.v alu_f.sby
alu: alu.vhd alu_t.sv alu_f.sby
sby -f -d work alu_f.sby

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