Trying to verify Verilog/VHDL designs with formal methods and tools
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  1. [tasks]
  2. cover
  3. bmc
  4. prove
  5. [options]
  6. depth 25
  7. cover: mode cover
  8. bmc: mode bmc
  9. prove: mode prove
  10. [engines]
  11. cover: smtbmc z3
  12. bmc: abc bmc3
  13. prove: abc pdr
  14. [script]
  15. ghdl --std=08 -gFormal=true -gDepth=16 -gWidth=16 fifo.vhd vai_fifo.vhd -e vai_fifo
  16. prep -top vai_fifo
  17. # Convert all assumes to asserts in sub-unit i_fifo
  18. chformal -assume2assert vai_fifo/i_fifo %M
  19. # Remove selected covers in i_fifo sub-unit as they cannot be reached
  20. chformal -cover -remove */formalg.read_pnt_stable_when_empty.cover
  21. chformal -cover -remove */formalg.rerror.cover
  22. chformal -cover -remove */formalg.werror.cover
  23. chformal -cover -remove */formalg.write_pnt_stable_when_full.cover
  24. [files]
  25. ../fifo/fifo.vhd
  26. vai_fifo.vhd