Trying to verify Verilog/VHDL designs with formal methods and tools
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18 lines
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6 years ago
6 years ago
6 years ago
  1. [options]
  2. depth 30
  3. wait on
  4. mode prove
  5. #mode bmc
  6. [engines]
  7. smtbmc
  8. abc pdr
  9. [script]
  10. verific -vhdl alu.vhd
  11. verific -formal alu_t.sv
  12. prep -top alu_t
  13. [files]
  14. alu.vhd
  15. alu_t.sv