Trying to verify Verilog/VHDL designs with formal methods and tools
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
|
|
- [options]
- depth 30
- wait on
- mode prove
- #mode bmc
-
- [engines]
- smtbmc
- abc pdr
-
- [script]
- verific -vhdl alu.vhd
- verific -formal alu_t.sv
- prep -top alu_t
-
- [files]
- alu.vhd
- alu_t.sv
|