tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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Add counter as example for initial reset problems

6 years ago

alu: counter.vhd counter_t.sv counter_f.sby
	sby -f -d work counter_f.sby


clean:
	rm -rf work