tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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Making counter design work with GHDL synthesis * Remove unused SVA properties file * Makefile optimizations * Use prep auto-top option to prevent error with not founded top-level module when using generics * Add some simple PSL assertions

5 years ago

Replace reset checks by async VHDL asserts; Add assumptions about inputs

4 years ago

Making counter design work with GHDL synthesis * Remove unused SVA properties file * Makefile optimizations * Use prep auto-top option to prevent error with not founded top-level module when using generics * Add some simple PSL assertions

5 years ago

[tasks]
cover
bmc
prove

[options]
depth 25
cover: mode cover
bmc: mode bmc
prove: mode prove

[engines]
cover: smtbmc z3
bmc: smtbmc z3
prove: smtbmc z3

[script]
ghdl --std=08 -gInitVal=23 -gEndVal=42 -fpsl counter.vhd -e counter
prep -auto-top

[files]
counter.vhd