Trying to verify Verilog/VHDL designs with formal methods and tools
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22 lines
268 B

[tasks]
cover
bmc
prove
[options]
depth 25
cover: mode cover
bmc: mode bmc
prove: mode prove
[engines]
cover: smtbmc z3
bmc: smtbmc z3
prove: smtbmc z3
[script]
ghdl --std=08 -gInitVal=23 -gEndVal=42 -fpsl counter.vhd -e counter
prep -auto-top
[files]
counter.vhd