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formal_hw_verification
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fifo: Fix SERE to also match cycles w/o ren after last write

master
T. Meissner 3 years ago
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@ -296,7 +296,7 @@ begin
GEN : if i = 0 generate GEN : if i = 0 generate
DATA_FLOW_GEN : assert always DATA_FLOW_GEN : assert always
{{s_cnt = i and Wen_i = '1' and Din_i = s_data} ; {Ren_i}}
{{s_cnt = i and Wen_i = '1' and Din_i = s_data} ; {not Ren_i[*]; Ren_i}}
|=> {Dout_o = s_data}; |=> {Dout_o = s_data};
else generate else generate


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