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@@ -108,10 +108,13 @@ begin
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108
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108
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default clock is rising_edge(Clk_i);
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109
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109
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110
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110
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-- Initial reset
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111
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- restrict {not Reset_n_i[*3]; Reset_n_i[+]}[*1];
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111
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+ RESTRICT_RESET : restrict
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+ {not Reset_n_i[*3]; Reset_n_i[+]}[*1];
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112
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113
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113
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114
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-- Inputs are low during reset for simplicity
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114
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- assume always not Reset_n_i -> not Wen_i and not Ren_i;
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115
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+ ASSUME_INPUTS_DURING_RESET : assume always
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116
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+ not Reset_n_i ->
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117
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+ not Wen_i and not Ren_i;
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115
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118
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116
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119
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117
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120
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-- Asynchronous (unclocked) Reset asserts
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