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formal_hw_verification
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13 Commits (195765a2aa640ba46ea9989e10e204d2b5de637e)

Author SHA1 Message Date
  T. Meissner 195765a2aa Adapt to use GHDL as plugin for Yosys VHDL synthesis 6 years ago
  T. Meissner c6cc9203d3 Add png versions of read/write waveform examples 6 years ago
  T. Meissner 8586d8a265 Add frame diagrams for write/read req/acks 6 years ago
  T. Meissner 2a090443ef Add waveforms of read/write examples 6 years ago
  T. Meissner 38ae7057c2 Incomment proof with abc pdr 6 years ago
  T. Meissner 9cb4b7d291 Replace integer coded FSM states by symbolic state names 6 years ago
  T. Meissner 8edb03c011 Add a bunch of new properties; name all assert directives 6 years ago
  T. Meissner 60e2c0f301 Add some more signals to trace 6 years ago
  T. Meissner b48e99c1f0 Simplify signal generation 6 years ago
  T. Meissner 4e30f44cb0 Fix req cai handling; add more properties 6 years ago
  T. Meissner 1deb6e9789 Add vai_reg to README; using SVA default clocking 6 years ago
  T. Meissner 63fc34f66a Add DoutValid_o to condition for state change in putput states 6 years ago
  T. Meissner a0f6a0b81d Add simple VAI register file as base to try to formal verify FSM designs 6 years ago