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formal_hw_verification
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7 Commits (3d29afb13d7ae537c6a431156ac93221bc8f2e6c)

Author SHA1 Message Date
  T. Meissner 3d57fff226 Replace reset checks by async VHDL asserts; Add assumptions about inputs 4 years ago
  T. Meissner f2f433b165 Use PSL functions instead of workarounds; add forgotten always to asserts in alu 5 years ago
  T. Meissner d94585cad8 Making counter design work with GHDL synthesis 5 years ago
  T. Meissner 5b8d9650e0 Add genric setting counter end value 6 years ago
  T. Meissner 9d03113704 Make the unbounded prove work 6 years ago
  T. Meissner dd0642e762 parameterize design; fix minor makefile problemswq 6 years ago
  T. Meissner 9d0198b0b4 Add counter as example for initial reset problems 6 years ago