formal_hw_verification

324 KiB

Tree: 3d29afb13d

Author	SHA1	Message	Date
T. Meissner	4a58b1789c	fifo: Add example for GHDL property replication * By replacing the goto operator with non-literal parameter by counting the read enabled with simple VHDL counters we can now replicate the properties instead of writing them all out. * Decrease the data width to decrease run-time of unbounded proofs	3 years ago
T. Meissner	c8c8062dca	Add data flow checks in fifo units	4 years ago
T. Meissner	705171911a	Add simple FIFO model incl. formal tests	4 years ago
T. Meissner	6c3a6db83b	Remove unused SVA properties file; Makefile optimizations; use prep auto-top option to prevent error with not founded top-level module	5 years ago
T. Meissner	367343cff5	Add make targets and SymbiYosys tasks for cover, bmc & prove	5 years ago
T. Meissner	195765a2aa	Adapt to use GHDL as plugin for Yosys VHDL synthesis	5 years ago
T. Meissner	38ae7057c2	Incomment proof with abc pdr	6 years ago
T. Meissner	a0f6a0b81d	Add simple VAI register file as base to try to formal verify FSM designs	6 years ago